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+# Advanced Computer Architectures - lesson 1
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+#### Cristiana Silvano
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+###### 7 March 2016
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+## Course Informations
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+
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+Download on the course sites the slides in advance
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+
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+## Course Topic
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+### Supercomputers
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+The most powerful supercomputer in italy is situated in Cineca institute in Bologna.
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+Actually the most powerful supercomputer in the world is situated in China
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+- __Tianhe-2__ 33.86 PetaFlops on Linpack (benchmark)
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+- __Titan__ 17.59 PetaFlops on Linpack (benchmark)
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+ - 80'000 NVIDIA Tesla GPUs
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+
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+### Exascale Supercomputers
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+- 20 MW projected to 2023 which requires 50GFlops/W
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+ For example Tianhe-2 is only 40th in the consumption list
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+The answer to exascale era are Summit and Sierra supercomputers developed in the USA
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+
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+### The topic of the course will be:
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+### Studying cpu architecture for supercomputers, desktop/server and embedded/mobile
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+
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+### example: Apple A6
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+- Introduced in 2012 for the iPhone 5
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+- Used Samsung fabrication technology (LoL)
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+
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+### Apple A9
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+- ARMv8 dual core CPU and six-core GPU
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+- Competing against Qualcomm Snapdragon 820 and Samsung Exynos 8890
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+- Manufactured 14nm by Samung and 16nm by TSMC
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+
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+### Energy Efficiency
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+- This includes squeezing of computer cores in smaller packages
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+- Every two year we can double the number of transistors per size
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+
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+#### We can build multi/may-cores architecture but we cannot switch on all of them together
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+This is the __Dark silicon era__
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+Power consumption and single thread performance are not excalating as density.
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+
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+### Pipelining in MIPS
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+Produced nowadays but Imagination technology (same as PowerVR GPU)
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+
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+#### MIPS Architecture
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+- RISC Instuction set
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+- LOAD/STORE Architecture, cannot operate directly on memory (need to load on registers)
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+```
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+example from C
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+c = a + b;
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+a -> $s1
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+b -> $s2
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+c -> $s3
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+
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+MIPS assembly
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+lw $s1,A($s6)
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+lw $s2,B($s6)
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+add $s3, $s1, $s2
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+sw $s3, C($s6)
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+```
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+#### Reduced MIPS assembly used:
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+- ALU operations
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+- LOAD/STORE
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+- branch/jump
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+
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+### ALU instructions
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+__R-format__
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+|op|rs|rt|rd|shamt|funct|
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+|---|---|---|---|---|---|
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+__I-format__
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+|op|rs|rt|immediate|
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+|---|---|---|---|
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+|6bit|5bit|5bit|16bits|
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+
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+### Load/Store instructions
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+__R-format__
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+|op|rs|rt|rd|shamt|funct|
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+|---|---|---|---|---|---|
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+__I-format__
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+|op|rs|rt|offset|
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+|---|---|---|---|
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+|6bit|5bit|5bit|16bits|
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+
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