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+# Advanced Operating Systems and Embedded Systems - exercise session 1
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+#### Davide Zoni
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+###### 13 October 2016
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+## Embedded Systems - Multicore Design
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+### Course structure
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+Multi core architectures require an interconnection layer to be exploited fully.
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+
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+The course is structured in three parts:
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+- On chip communication
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+- Architectural simulation
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+ Used to test architectural solutions without designing a complete RTL architecture.
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+- RTL Design Verification and Simulation
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+
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+This course will be focused mainly on the power requirements, not covering power, reliability and timing
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+for lack of time.
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+
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+__Exam structure__
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+Written exam: 23 points
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+Project + presentation: 9 points
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+
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+## Multi-core history
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+From 2000-2005 the CPUs development began hitting the "frequency wall"
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+And the power consumption and single thread performance limits aswell.
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+
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+But the market demands for more processing power, so the response
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+was development of the multi-core architecture.
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+
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+#### Market and Energy Efficiency
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+We have two conflicting needs.
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+The market asks for devices that are able to run the same applications no
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+matter what the underlying hardware.
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+while the technology viewpoint says that on mobile phones we have limited resources,
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+for example battery, so it's not easy to raise performance.
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+
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+__Reference book__: Low Power Methodology Manual, ARM&Synopsis, 2007
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+
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+Halving the size of transistor does not halve the power consumption,
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+so reducing size brings to increasing the power density.
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+
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+## Realiability
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+
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+#### Escape Bugs:
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+They are bugs that ship with the device, due to improper design, and they produce
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+a different results from the specification.
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+Simple architectures have less escape bugs, and usually the number rises as user discovers them.
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+#### Hard Faults:
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+Hardware damage due to not proper usage, ex: overvolting.
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+
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+To test an architecture for escape bugs you have to try all the inputs for all the possible states, because
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+usually the CPUs are not *stateless*
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+5Million flip-flops means 2^5million states.
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+Usually __Bug Inspection__ is done partitioning the design and testing the more common states to be bug-free
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+This testing is constrained by time-to-market. But later the verified portion can be expanded.
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+
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+### Multi-cores
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+In general it is more likely to have multiple applications using few resuources, than a single application
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+using more resources.
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+
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+## On-chip interconnects
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+Usually the main types of traffic on *on-chip interconnections* are:
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+- Data from *load* and *store* OPs
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+- Data for cache coherence.
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+
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+### Different Architectures
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+- __Point-to-point__ Used by intel since 2010 in i5 CPUs
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+It is fast and simple but grows with n\*(n-1) to the number of cores
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+
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+- __Bus__ Simple but usually need a split architectures, for example a bus between
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+CPU+L1 and L2 and a slower one between L2 and memory.
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+
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+- __Crossbar__ is a non-blocking architectures until two sender are reaching the same destination
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+or vice versa.
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+The crossbar is no more than a *multi-bus* architecture, it can be *full* or not.
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+The idea is that the more bus used, the more power consumption we have.
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+
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+- __Network-on-chip__:
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+
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+
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+## On-chip Bus Architecture
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+The bus is manager by an __arbiter__ that is not shown usually on schemes.
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+
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+The bus is not a single line/wire a shown in theory
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+In fact there are three different architectures:
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+- Tri-state:
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+- AndOr:
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+- Mux: is the most common, it does not have native broadcast support, it can scale better
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+but if i want to send a broadcast message (ex: for snooping) i have to consume more power.
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+
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+The BUS is the ideally placed in the between of the cores, to reduce the length of the wires.
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+The BUS has also to avoid __deadlock__ situations.
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+
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+A __bridge__ is a piece of hardware that interfaces two different communication protocols.
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+
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